1. Field of the Invention
The present invention relates generally to storage device controllers, and more particularly, to processing frames.
2. Background
Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives).
In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
The storage device is coupled to the host system via a controller that handles complex details of interfacing the storage devices to the host system. Communications between the host system and the controller is usually provided using one of a variety of standard I/O bus interfaces.
Typically, when data is read from a storage device, a host system sends a read command to the controller, which stores the read command into the buffer memory. Data is read from the device and stored in the buffer memory. Buffer memory may be a Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (referred to as “DDR” or “SDRAM”)).
Storage controllers use various standards to move data frames in and out of storage devices. One such standard is the Fibre Channel standard. Fibre channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others.
A storage controller may receive various types of frames, for example, data, link or command frames. Task management requests (“TMRs”) per the Fibre Channel protocol, provide an option to take action for a command thread that may be residing in buffer memory of the storage controller. A TMR is a command frame that includes task management flags. If a command buffer is full, then the TMR may also be encoded as a link frame.
Some conventional storage controllers store data, link, command and TMRs in sequential order and execute and process them as they are being received. This approach has disadvantages because it results in latency and delays.
Conventional storage systems may also use a timer to evaluate, execute and flush command frames from a queue. This requires additional logic and makes the process complex and expensive.
Therefore, there is a need for a system and method that can efficiently handle command frames and TMRs.